1. Field of the Invention
The invention relates generally to Ethernet controllers, and in particular, a method for using a delay on a transmit complete interrupt only on small sized packets.
2. Background Information
Personal computers (PCs), servers, printers, and other such devices (sometimes referred to as xe2x80x9cdata terminal equipmentxe2x80x9d or DTE) are often connected together as a network or LAN. Many LANs operate according to Ethernet standards and protocols. FIG. 1 shows such a LAN 101. With Ethernet technology, all DTEs 103 in the LAN share the bandwidth of a communication medium 105 (e.g., twisted pair or coaxial cables) that connects the DTEs 103 together. All DTEs 103 in the LAN are reached anytime there is a single transmission of data in the form of xe2x80x9cEthernetxe2x80x9d frames having source and destination addresses. Only the DTE 103 having the destination addresses processes the received transmission. Ethernet networks are known as xe2x80x9cconnectionlessxe2x80x9d networks because by using source and destination addresses, communication can occur without the need to first establish a connection and without immediate acknowledgement of receipt.
PCs and other devices are connected to the LAN by various Ethernet hardware interfaces installed in or coupled to these devices. For example, many PCs are equipped with Network Interface Cards (NIC) 107, such as the commonly used Ethernet NIC card and various Ethernet controller units. The terms Ethernet controller, NIC, and Ethernet NIC are synonymous as used herein. An Ethernet LAN often uses carrier sense multiple access with collision detection (CSMA/CD) methods, where different nodes listen for transmissions in progress in the communication medium before beginning to transmit.
During the reception or transmittal of Ethernet packets, the NIC must request resources from the central processor unit (CPU) of its host device. The resources may include, for example, the system bus, input/output ports, or memory. Once the transmit or receipt function is complete, the NIC may release some of the allocated resources. When a packet is received, a receive complete interrupt is generated from the NIC to the host device""s CPU to inform the CPU that the NIC needs to copy the received packets into the host device""s memory.
When a transmit of an Ethernet packet is complete, the NIC will generate an interrupt to the host device""s CPU in order to inform the CPU that the NIC is ready to release the resources that it used to transmit the packet. This interrupt is referred to as a xe2x80x9ctransmit complete interruptxe2x80x9d or TxCI.
In certain cases, the TxCI is not sent by the NIC immediately upon completion of the transmittal of the Ethernet packet. Instead, a delay is imposed before the transmit complete interrupt is forwarded to the CPU. This is referred to as a transmit complete interrupt delay (TxCID). This is done because the CPU overhead associated with the transmit complete interrupt is very high. In the prior art, the TxCID is constant for all Ethernet packets.